MIPS critical path of a branch instruction
Suppose I have a MIPS processor performing a
beq instruction e.g.
beq $t1, $t2, label
I'm trying to figure out the critical path of this instruction. Suppose every component has the same delay. My idea for the critical path is as follows:
Path 1: Add -> ............ -> Add -> Mux Path 2: IM -> Control -> Mux -> ALU -> Mux Path 3: IM -> Registers -> Mux -> ALU -> Mux
How do I go about filling in the rest of Path 1 (or other paths if they're wrong) considering it has to wait for some signals to be ready?
Also is there any reason why path 3 would not be the critical path if we assume the delay of all components is the same (and ignore the gate delays)?
If you want to be able to compare paths, pick ONE point that all the paths of interest must go through, and start your counting from there in each path. In your case the simplest and most obvious one point is probably the PC latch, as that's the leftmost thing on your diagram. The paths will all be loops that start at that point, go through various blocks and all finally end up back at the same point for the next instruction.
If a path has to wait on singals from some other path, then it's not the critical path -- the path that it is waiting on is more critical. The (most) critical path will be the one that doesn't have to wait for any signals from other paths as those other signals will always be there before the critical path gets there.